PCB Thermal Via Array Design and Copper Plane Heat Spreading for SMT Power Devices

Thermal Management Challenge in SMT Power Devices

SMT (Surface Mount Technology) power devices — MOSFETs, IGBTs, DC-DC converters, and voltage regulators — dissipate significant heat through small footprint pads on the PCB. Unlike through-hole power components with large leads acting as thermal paths, SMT devices rely almost entirely on the PCB copper layers and thermal via arrays beneath their thermal pads to conduct heat away from the semiconductor junction.

The thermal resistance from junction to ambient (RθJA) for an SMT power device is determined by three key PCB design elements:

• Thermal pad copper area: The top-layer copper pour directly under the device’s thermal/ground pad
• Thermal via array: Plated-through vias co

  ecting the top thermal pad to i

  er/bottom copper planes

• Heat spreading copper planes: Large internal or bottom-layer copper areas that distribute heat across the PCB surface for convective cooling

This article provides a systematic design methodology for thermal via arrays and copper plane heat spreading, with calculation methods, design rules, and practical recommendations for optimizing SMT power device thermal performance.

Thermal Via Fundamentals

How Thermal Vias Work

A thermal via is a plated-through hole (PTH) that creates a vertical copper conduit from the top PCB layer (where the SMT device sits) to i

er or bottom copper layers. Each thermal via’s thermal conductivity depends on:

• Via diameter: Larger diameter = more copper wall area = lower thermal resistance per via
• Copper plating thickness: Thicker plating (1–2 oz, 35–70 μm) = more cross-sectional copper = better conduction
• Via fill: Copper-filled vias (via-in-pad) eliminate air gap inside the via, reducing thermal resistance by 3–5× compared to hollow plated vias

Single Via Thermal Resistance Calculation

The thermal resistance of a single plated-through via is calculated as:

R_via = L / (k_Cu × A_Cu)

Where:

• L = via length (PCB thickness, typically 1.0–1.6 mm)
• k_Cu = copper thermal conductivity ≈ 385 W/(m·K)
• A_Cu = copper cross-sectional area in the via wall

For a 0.3 mm diameter via with 25 μm (1 oz) plating in a 1.6 mm thick PCB:

A_Cu = π × (d_outer² – d_i

er²) / 4 = π × (0.3² – 0.25²) / 4 ≈ 0.0218 mm²

R_via = 0.0016 / (385 × 0.0218 × 10⁻⁶) ≈ 190°C/W per via

Copper-Filled Via Thermal Resistance

For a 0.3 mm copper-filled via in the same 1.6 mm PCB:

A_Cu = π × 0.3² / 4 ≈ 0.0707 mm²

R_via = 0.0016 / (385 × 0.0707 × 10⁻⁶) ≈ 59°C/W per via

Key insight: Copper-filling reduces single via thermal resistance by approximately 3.2×. For thermal via arrays, this translates to dramatically lower total thermal resistance with fewer vias.

Thermal Via Array Design Methodology

Via Spacing and Array Geometry

The total thermal resistance of a via array depends on the number of vias and their arrangement. Common array patterns include:

• Grid pattern: Regular rows and columns — most common, easy to design, predictable thermal resistance
• Radial pattern: Vias arranged concentrically around the device center — better for circular thermal pads
• Staggered pattern: Offset rows — allows slightly higher via density than regular grid

Minimum Via Spacing Rules

Array Thermal Resistance Calculation

For N vias in parallel, the total array thermal resistance is:

R_array = R_via / N

For 20 hollow plated vias (each 190°C/W) under a QFN power device thermal pad:

R_array = 190 / 20 ≈ 9.5°C/W

For 20 copper-filled vias (each 59°C/W):

R_array = 59 / 20 ≈ 3.0°C/W

Practical significance: For a MOSFET dissipating 2W with 20 copper-filled thermal vias, the via array contributes only 6°C temperature rise — a manageable contribution to the total RθJA.

Copper Plane Heat Spreading Design

Top-Layer Thermal Pad Area

The top-layer copper pour directly under the SMT power device serves as the first heat spreading stage. Design considerations:

• Minimum pad area: At least 2× the device thermal pad footprint — heat spreads radially, and the pad must extend beyond the device outline to provide meaningful spreading
• Pad shape: Square or rectangular pads aligned with the PCB grid — circular pads waste board area and complicate routing
• Solder mask coverage: No solder mask on the thermal pad area — solder mask (k ≈ 0.2 W/(m·K)) acts as thermal insulation between the device and the copper
• Thermal relief vs direct co

  ect: For power devices, always use direct co

  ect (no thermal relief spokes) — thermal relief pads add 40–60% resistance to the thermal path

I

er Layer Copper Planes

I

er copper planes co

ected by thermal vias provide the second heat spreading stage:

• Plane area requirement: Minimum 10× the device thermal pad area for effective spreading. A 5×5 mm device pad should co

  ect to at least a 50×50 mm i

  er plane

• Plane thickness: 1 oz (35 μm) minimum; 2 oz (70 μm) for devices dissipating >3W. Thicker copper provides both better lateral heat spreading and lower via-to-plane interface resistance
• Plane continuity: Avoid splitting the thermal plane with signal traces — every split creates a thermal bottleneck. Route signals on other layers instead
• Multiple plane layers: Co

  ecting thermal vias to both an i

  er ground plane and the bottom copper layer provides two parallel heat spreading paths, reducing overall thermal resistance by 30–50%

Heat Spreading Physics — The 45° Rule

Heat from a small source (device pad) spreading through a thin copper plane follows approximately the 45° spreading angle: the effective heat collection area expands by about 1× the copper thickness per unit distance from the source edge.

For a 35 μm (1 oz) copper plane with a 5×5 mm thermal pad:

• At 5 mm from pad edge: effective area ≈ 10×10 mm (pad + 5 mm spreading on each side)
• At 10 mm from pad edge: effective area ≈ 15×15 mm
• At 35 mm from pad edge: spreading reaches its practical limit (≈0.7× plane thickness per mm stops being significant)

Design implication: For 1 oz copper, thermal plane area beyond approximately 40 mm from the device pad edge contributes negligible additional heat spreading. Use 2 oz copper to extend effective spreading to ≈70 mm, or add thermal vias to co

ect to multiple layers for wider distribution.

Combined Thermal Resistance Model

RθJA Stack-Up for SMT Power Device on PCB

Total RθJA Calculation Example

For a 2W QFN MOSFET with:

• RθJC = 2°C/W (device spec)
• Solder interface = 1°C/W
• Top pad (10×10 mm, 2 oz) = 1.5°C/W
• 25 copper-filled thermal vias (0.3mm, 1.6mm PCB) = 2.4°C/W
• I

  er 2 oz plane (50×50 mm) = 8°C/W

• Natural convection from both PCB surfaces = 25°C/W

RθJA ≈ 2 + 1 + 1.5 + 2.4 + 8 + 25 ≈ 40°C/W

T_junction = T_ambient + P × RθJA = 25°C + 2W × 40°C/W = 105°C

For a device rated to 150°C junction, this leaves 45°C margin — acceptable for most applications.

Practical Design Optimization Strategies

Via Optimization

1. Use copper-filled vias (via-in-pad) for any device dissipating >1W — the 3× thermal improvement justifies the cost premium ($0.01–0.03 per via)
2. Maximize via count within spacing rules — fill the thermal pad area with vias at minimum spacing. The R_array formula (R_via/N) makes every additional via directly beneficial
3. Extend vias beyond the device pad: Add vias in the top copper pour surrounding the pad — these vias conduct heat that has already spread laterally in the top layer, providing additional paths to i

   er planes

4. Co

   ect vias to multiple planes: Route via co

   ections to both an i

   er ground plane AND the bottom layer — this doubles the heat spreading surface area

Plane Optimization

1. Use 2 oz i

   er planes for thermal layers — the 2× thickness improvement in lateral conductivity outweighs the cost increase

2. Keep thermal planes unbroken: Dedicate one i

   er layer entirely to the thermal/ground plane. Route all signals on other layers

3. Extend plane beyond device area: Minimum 10× device pad area. In constrained designs, co

   ect the thermal plane to adjacent ground fills with thermal reliefs (ironic — thermal reliefs on the spreading plane boundary, not at the device pad)

4. Bottom-layer copper pour: Make the entire bottom layer a ground/thermal pour, only clearing signal trace routing — maximum convective surface area

Southeast Asian Environmental Factors

• Higher ambient temperature: 35–40°C typical operating environment vs 25°C in datasheet calculations — reduces thermal margin by 10–15°C at the same power dissipation
• Humidity condensation risk: Thermal via arrays can trap moisture — conformal coating or via plugging prevents moisture ingress in high-humidity environments
• Convection limitation: Enclosed device housings in tropical environments reduce natural convection efficiency by 30–50% — plan for forced airflow or heatsink attachment

Conclusion

Effective thermal via array design and copper plane heat spreading are the two most impactful PCB-level decisions for SMT power device thermal management. The formula is straightforward: maximize via count with copper fill under the thermal pad, co

ect those vias to thick (2 oz) unbroken i

er copper planes extending at least 10× the pad area, and ensure the bottom PCB surface provides maximum convective cooling area. For electronics designs serving Southeast Asian markets where ambient temperatures run 10–15°C above datasheet assumptions, these optimizations are not optional refinements — they are essential design practices that determine whether a power device operates within its rated junction temperature or fails prematurely from thermal overstress.