Tombstoning — also called the Manhattan effect or drawbridge effect — occurs when a small surface-mount component (typically 0402 or smaller chip capacitors/resistors) stands vertically on one end during reflow, creating an open circuit on the other pad. It is one of the most common SMT defects and can be largely eliminated through design and process control.
The Physics Behind Tombstoning
Tombstoning is driven by surface tension imbalance. When one end of a component melts before the other, the liquid solder on the molten side contracts and exerts an upward rotational force. If this force exceeds the component weight and the mechanical resistance of the still-solid solder on the other end, the component rotates upright.
The phenomenon is more pronounced with smaller, lighter components (0201, 01005), asymmetric pad geometries, thermal imbalance between the two pads, and high-activity flux that melts solder aggressively.
Root Causes by Category
PCB Layout and Pad Design
Pads of unequal size create different solder volumes on each end. The larger pad has more solder mass and takes longer to melt, creating the temperature differential that drives tombstoning. IPC-7351 land pattern recommendations account for this — follow them closely for 0402 and smaller components.
Stencil and Paste Volume
Over-printing one pad relative to the other amplifies the solder volume imbalance. Ensure aperture openings are symmetric and the stencil is properly aligned. Aspect ratios below 1.5 on either aperture increase the risk of inconsistent paste deposition and should be avoided.
Reflow Profile
An insufficient soak zone is a primary process cause. When components do not thermally equalize before entering the reflow zone, temperature gradients across a single component leads directly to tombstoning. Extend the soak at 150-180°C for 60-90 seconds to eliminate this gradient.
Prevention Checklist
- Use IPC-7351 compliant land patterns for all chip components
- Verify stencil aperture symmetry before production runs
- Extend soak zone to equalize thermal mass across components
- Orient chip components perpendicular to oven conveyor direction
- Minimize thermal shadow effects from adjacent large components
- Use low-residue, no-clean flux with moderate activity level
Tombstoning rates above 50 ppm typically indicate a systemic design or process issue. With proper pad design and a well-tuned reflow profile, rates below 10 ppm are achievable on even the smallest chip components in volume production.
